Boise State University Electrical Engineering

Syllabus for EE410 Integrated Circuit Physical Design

Fall Semester 1999

Description: CMOS IC schematic capture, circuit simulation, layout, design-rule checking, and parasitic capacitance extraction, using CADENCE layout and simulation tools. Design of static and dynamic logic gates, sequential logic, and latches. Final design projects will be fabricated by a MOSIS SCMOS foundry. PREREQ: Semiconductor Devices and Electronic Circuits; EE320 and EE322.

Textbooks:

• J. M. Rabaey, Digital Integrated Circuits, A Design Perspective, Prentice-Hall 1996. Homepage: http://infopad.eecs.berkeley.edu/~icdesign
  
• R.J. Baker, H.W. Li, and D.E. Boyce, CMOS Circuit Design, Layout & Simulation, IEEE Press, 1997.

Course Homepage:

• http://appliance.boisestate.edu/ee410

Professor:

• Ken Boorom
• E-Mail: ken_boorom@hp.com
• Phone: 396-7905
• FAX: 396-7060

Lectutres:

• BSU: SMITC118 (Simplot/Micron Center) on Mondays & Wednesdays at 2:40-3:30pm
• CABLE: Channel 39, Mondays & Wednesdays, 2:40 - 3:30pm. Reruns from 8:00-8:50pm
• Several weeks of videotapes are available in BSU's Albertson's Library

Labs:

• BSU: ET212 CAD Lab on Fridays at 2:40-4:30 PM
• Off-Campus: OK if you have software and good technical support

Goals:

1. Design and schematically capture combinatorial and sequential CMOS integrated circuits using CADENCE design tools.
2. Simulate these circuit designs to verify functionality, speed, and power dissipation using BSIM MOSFET device models.
3. Layout custom circuits that implement a given schematic while passing all design rules, using CADENCE design tools.
4. Be able to discuss intelligently the various interactions between devices, processes and the design process.

Topics:

1. Combinatorial logic, both static, dynamic and low-power approaches
2. IC design process from silicon level layout to HDL level system design, illustrating current industry examples of design tools at each level of the design heirarchy
3. Review of MOS devices and SPICE device models: Level 1 to BSIM3.
4. Basic NMOS and CMOS inverter DC analysis, transfer characteristics
5. Parasitic capacitance and resistance calculations for interconnect delay
6. Performance, Power Dissipation, Area Tradeoff calculations
7. Combinatorial logic, both static, dynamic and low-power approaches
8. JK flip-flops, sequential logic, race conditions, NORA logic

Computer Usage:

• Extensive use of UNIX workstations for homework and design project, using schematic capture, SPICE simulation, layout, and DRC software.
• Cadence Design Framework II toolset (Spectre, Composer, Virtuoso, Analog Artist)

Grading:

• 3 Homeworks = 10%
• 5 Labs = 20%
• 7 Quizzes (lowest 2 grades dropped)=20%
• Project = 30%
• Final = 20%

Project Grading:

• 10 points - Project Proposal
• 20 Points - Final Project
• 90% of grade is on you work, 10% on group's work

Late Policy for Homeworks/Labs:

• 1 day late = 10% off
• 2 days late=30% off
• Not accepted more than 3 days late

Makeup Quizzes:

• I drop your lowest 2 grades, so makeup quizzes are not given

Approximate Schedule: (Add 1 or 2 floater lectures for guest lecturers)